Model/Brand/Package
Category/Description
Inventory
Price
Data
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Category: logic chipDescription: 2.5V / 3.3VSiGe differential receiver/driver with variable output swing of 2.5V/3.3V11641+$139.063810+$135.436050+$132.6547100+$131.6873200+$130.9618500+$129.99441000+$129.38982000+$128.7851
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Category: logic chipDescription: 2.5V / 3.3V 12 Gb / sDifferential clock/data Smartgate with CML output and internal terminal 2.5 V/3.3V 12 Gb/s Differential Clock/Data SmartGate with CML Output and Internal Termination8301
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Category: logic chipDescription: Logic IC - Multivibrator NXP Semiconductors 74AHCT123ABQ, 115 Monostable 5ns DHVQFN 16 (2.5x3.5)37045+$1.476925+$1.367550+$1.2909100+$1.2581500+$1.23622500+$1.20895000+$1.197910000+$1.1815
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Category: logic chipDescription: 2.5V / 3.3V ?SiGe Differential Smart Gate with Output Level Selection 2.5V/3.3VSiGe Differential Smart Gate72141+$250.818510+$244.275450+$239.2590100+$237.5142200+$236.2055500+$234.46071000+$233.37022000+$232.2797
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Category: logic chipDescription: 74LV123 Series 1-5.5 V Dual Channel Re Triggered Single Steady State Multi Harmonic Oscillator - DHVQFN16864010+$1.078750+$1.0227100+$0.9828300+$0.9588500+$0.93481000+$0.91092500+$0.87495000+$0.8669
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Category: logic chipDescription: Monostable Multivibrator Dual 16Pin DHVQFN EP T/R563410+$1.028750+$0.9754100+$0.9373300+$0.9144500+$0.89151000+$0.86872500+$0.83445000+$0.8268
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Category: logic chipDescription: 2.5V / 3.3V 12 Gb / sDifferential clock/data Smartgate with CML output and internal terminal 2.5 V/3.3V 12 Gb/s Differential Clock/Data SmartGate with CML Output and Internal Termination2137
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Category: logic chipDescription: 2.5V / 3.3V , 12GB / sMulti level clock/data input to RSECL, high gain receiver/buffer/converter with internal termination 2.5 V/3.3V, 12Gb/s Multi Level Clock/Data Input to RSECL, High Gain Receiver/Buffer/Translator with Internal Termination7009
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Category: logic chipDescription: 3.3V , 2.5Gb / sDual AnyLevel ⑩ to LVDS receiver/driver/buffer/converter with internal input terminal 3.3V, 2.5Gb/s Dual AnyLevel ⑩ to LVDS Receiver/Driver/Buffer/Translator with Internal Input Termination5494
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Category: logic chipDescription: 2.5V / 3.3V , 12GB / s的多级时钟/数据输入到RSECL ,高增益接收器/缓冲器/转换器具有内部端接 2.5V/3.3V, 12Gb/s Multi Level Clock/Data Input to RSECL, High Gain Receiver/Buffer/Translator with Internal Termination8573
